Technical Field
Embodiments described herein are related to electrostatic discharge (ESD) protection in integrated circuits.
Description of the Related Art
The transistors and other circuits fabricated in semiconductor substrates are continually being reduced in size as semiconductor fabrication technology advances. Such circuits are also increasingly susceptible to damage from ESD events, thus increasing the importance of the ESD protection implemented in integrated circuits. Generally, ESD events occur due to the accumulation of static charge, either on the integrated circuits themselves or on devices or other things that come into contact with the integrated circuits. Entities such as humans can also accumulate static charge and cause ESD events when coming into contact with an integrated circuit or its package.
A sudden discharge of the static charge can cause high currents and voltages that can damage the integrated circuit, and the potential for damage is higher with smaller feature sizes. There are various models for ESD events, which integrated circuit designers use to design and evaluate ESD protection circuits. For example, the charged device model (CDM) models the discharge of static electricity accumulated on the integrated circuit itself. The human body model (HBM) models the discharge of static electricity from a human body touch on the integrated circuit. Other models may be used for other types of ESD (e.g. the contact of various machines during manufacturing, etc.).
Typical ESD protection circuits for integrated circuits include diodes that are connected between integrated circuit input/output signal pin connections and power/ground connections. The diodes and other protection circuits are designed to turn on if an ESD event occurs, rapidly discharging the ESD event to avoid damage to the functional circuits (e.g. driver/receiver transistors) that are coupled to the pin connections. The ESD circuits are designed to withstand the maximum currents/voltages of various ESD events, according to a specification to which the integrated circuit is designed.
When a load-sensitive circuit (e.g. a high speed analog circuit) is integrated into a larger integrated circuit, the size of the ESD devices presents significant design challenges. The large ESD devices load the pins, reducing performance of the high speed circuit. The large ESD devices also consume significant area. Furthermore, the need to size the devices based on the size of the complete integrated circuit and/or its packaging (e.g. for CDM ESD protection) makes the reuse of the circuit in different integrated circuit designs problematic.